According to the Semiconductor Industry Association, nearly two-thirds of the world’s industrial electricity is used to run motors. However, only 5 percent of these motors use variable-speed drives (see Figure 1). The other 95 percent waste a large amount of energy. Switching to electrical motors that use variable-speed drives could save 68 million tons of greenhouse gases, the equivalent of 10 power plants, annually.

Figure 1: Today’s usage of the world’s industrial electricity (click graphic to zoom by 1.9x)

By applying semiconductor technology to motor control, industrial applications can realize energy efficiencies of up to 88 percent. The function of the motor controller is to limit the motor’s output. A digital speed controller does this by controlling the motor’s electrical drive, thus minimizing overall energy consumption as well as reducing wear and tear on the mechanical parts. In addition, high-efficiency motors deliver significant savings in energy consumption and limit carbon emissions.

Motion control trends

Two major trends are helping drive the growth of motion control applications:

1.  Industrial systems including motion control solutions operate across industrial communication networks, whether the medium is legacy fieldbus or the new Industrial Ethernet protocol standards. Factories implement multiple Ethernet standards on the plant floor, driving an annual growth rate of 51 percent for Industrial Ethernet devices by 2011.

2.  The industry is increasingly adding safety to automation and motion/drive control solutions; it is estimated that the latter will be up to 70 percent safer within five years. Safety in motion control will help save lives and minimize investment loss caused by damage that occurs on the factory floor due to equipment failures.

FPGAs are playing an increasing role in motion control, where they can offer the flexibility to control different types of motors within industrial networks. The virtues of FPGAs in industrial applications are based on these two major industry trends that contribute to the growth of motion control applications.

The true advantage of using FPGAs is the ability to customize what was previously fixed generic hardware in MCUs or DSPs. In FPGAs the standard Pulse-Width Modulated (PWM) block found in an MCU- or DSP-based motor control chip can be replaced by an application-specific PWM IP core optimized for performance and energy efficiency based on individual motor parameters.

The design separation approach

High-reliability system design requires reduced system size, power, and cost while maintaining expected reliability. Traditionally, high-reliability systems designs have approached reliability through redundancy (Figure 2). This redundancy manifests itself through increased component count, logic size, system power, and cost.

Figure 2: Redundancy in industrial motor control (click graphic to zoom by 1.9x)

Like motion control, these high-reliability applications currently require at least two chips so that the logic remains separate and functions independently. This ensures that a fault detected in one device does not affect the remainder of the application. FPGAs can be used to design for redundant functionality or multiple blocks of secure information inside a single FPGA.

A new software feature, which Altera refers to as design separation, gives design engineers the capability to create multiple blocks inside the FPGA that are independent and secure from the other user logic. In cases where design separation can be critical, such as industrial systems where entire manufacturing lines could be shut down if one piece of equipment fails, redundant circuits continue to control the system in the event of one circuit failing, guaranteeing little to no downtime.

Design separation allows designers to keep critical functions set apart within a single FPGA. This separation is accomplished through Quartus II design software, which permits designers to allocate design partitions to a specific section of the Cyclone III LS FPGA. Combining the new FPGA and design separation software feature makes it easy for design engineers to create redundant and secure logic within a single FPGA.

When the design separation flow based on incremental compilation is enabled as shown in Figure 3, each secure partition has an automatic fence or “keep out” region associated with it. In this way, no other logic can be placed in the proximity, creating one level of increased fault tolerance.

Figure 3: Design separation for high reliability and information assurance (click graphic to zoom by 1.9x)

However, to enable true separation, the routing must also be separated, which means that the fence region is composed of of unused logic and routing, providing a barrier through which glitches or errors cannot pass through to any other functional block within the device. This is effectively the same as using two physical devices to ensure separation. The design separation flow also enables specific banking rules that ensure the separation created in the fabric for critical design partitions extends to the I/O, enabling more than 80 percent of the design resources.

Other system design areas share these same reliability requirements and attributes. For example, the scenario is similar in information assurance applications; at least two chips are required to ensure independent functions. Again, when design separation is critical, such as in financial applications where data must be encrypted, data must not be allowed to leak from one portion of the design to an unsecured portion in the event of an inadvertent path created by a fault. This ensures that critical information is secure.

For green, one FPGA is better than two

High-reliability and information assurance systems share many design requirement similarities. Both systems require design separation and independence, as each system demands redundancy to ensure proper design operation in the event of hardware faults. Traditionally, implementing redundancy increases system size, weight, power, and cost because it is implemented at the board level. To reduce these factors, low-power FPGA processes can be used with a high-assurance design flow to meet stringent design requirements.

By ensuring design separation and independence, redundant logic can be transferred from the board level to a single FPGA device as part of a System-on-Chip (SoC) design approach. Combining low power, high logic density, and design separation features allows developers of high-reliability industrial systems to minimize design development, schedule risk using reprogrammable logic, improve productivity using a proven incremental compile design flow, and decrease power requirements, thus reducing energy usage.

At the current pace, it is inevitable that world energy supplies will be exceeded by the increased demand for technology. In this century and beyond, companies will not only need to compete on performance and price, but also on the amount of energy required to operate the equipment. Design engineers will be continuously challenged to decrease energy consumption in their designs. Selecting components such as FPGAs will provide a solution that can reduce system size, power, and cost, all of which will be tied to the energy efficiency and savings of industrial systems and a broad range of other types of applications.

The bottom line is that accomplishing these functions with one FPGA instead of two would conserve energy (I/O power), theoretically saving as much as 50 percent of the power being consumed in this aspect of the design. Combine this with highly energy-efficient power supplies and other techniques, and the end product could dramatically reduce the quantity of energy being consumed by inefficient industrial motors as well as seriously decrease the amount of greenhouse gases being emitted.

Tom Schulte is senior manager of low-cost products at Altera Corporation, based in San Jose, California, where he is responsible for product technical analysis and development strategies around Altera’s Cyclone FPGA and MAX CPLD product families. Prior to working at Altera, he served as a product engineer in IDT’s Subsystems Division. Tom holds a BS in Electrical Engineering from Santa Clara University.

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