With the world going “small” and “green,” and users demanding ever-more functionality and computing power in everything from mobile phones and iPods to multicore[]-based servers, power-aware design and the need to relentlessly cut power consumption has arguably become the most important issue facing system-on-chip (SoC) designers today. This webcast, sponsored by Cadence Design Systems, Inc. and Sonics, Inc., and moderated by John Miklosz, Editor-in-Chief of SOCcentral.com, will examine the methodologies and tools available — from the initial analysis and estimation of a design’s power consumption, to the implementation and trade-offs in power-reduction approaches, to the final verification and sign-off that a design has achieved the designer’s low-power intent — within the framework of the Common Power Format (CPF). The presentations will look at techniques such as clock gating, voltage islands, power gating, dynamic frequency scaling (DFS), dynamic voltage scaling (DVS), and adaptive voltage scaling, and the increasing role that on-chip interconnect solutions for communicating between clock and voltage domains play in reducing power consumption.

Presented by: Cadence Design Systems, Inc., Sonics, Inc.